Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, and various signal processing circuits.
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual images for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
FIG. 1 illustrates electronic device 50 having a chip carrier substrate or PCB 52 with a plurality of semiconductor packages mounted on a surface of the PCB. Electronic device 50 can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. Different types of semiconductor packages are shown in FIG. 1 for purposes of illustration.
Electronic device 50 can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device 50 can be a subcomponent of a larger system. For example, electronic device 50 can be part of a tablet, cellular phone, digital camera, or other electronic device. Alternatively, electronic device 50 can be a graphics card, network interface card, or other expansion card that can be inserted into a computer. The semiconductor packages can include microprocessors, memories, application specific integrated circuits (ASIC), programmable logic circuits, analog circuits, radio frequency (RF) circuits, discrete devices, or other semiconductor die or electrical components.
In FIG. 1, PCB 52 provides a general substrate for structural support and electrical interconnect of the semiconductor packages mounted on the PCB. Conductive signal traces 54 are formed over a surface or within layers of PCB 52 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces 54 provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces 54 also provide power and ground connections to each of the semiconductor packages. A clock signal is transmitted between semiconductor packages via traces 54.
In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. Second level packaging involves mechanically and electrically attaching the intermediate substrate to the PCB. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB.
For the purpose of illustration, several types of first level packaging, including bond wire package 56 and flipchip 58, are shown on PCB 52. Additionally, several types of second level packaging, including ball grid array (BGA) 60, bump chip carrier (BCC) 62, land grid array (LGA) 66, multi-chip module (MCM) 68, quad flat non-leaded package (QFN) 70, quad flat package 72, embedded wafer level ball grid array (eWLB) 74, and wafer level chip scale package (WLCSP) 76 are shown mounted on PCB 52. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB 52. In some embodiments, electronic device 50 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.
A manufacturer of electronic device 50 provides a clock signal to each semiconductor package to operate the synchronous logic elements within each package. Digital circuits of the semiconductor packages include flip-flops or latches which operate on edges of the clock signal. A binary digital value is either a logic zero or a logic one. A clock signal rapidly fluctuates between a logic zero and logic one. When a clock signal transitions from a logic zero to a logic one, the transition is a rising edge of the clock signal. When a clock signal transitions from a logic one to a logic zero, the transition is a falling edge of the clock signal.
Digital circuits formed on semiconductor die within semiconductor packages include flip-flops which store an input value of the flip-flop to the output of the flip-flop when a clock edge occurs. A flip-flop holds the output value until the next clock edge, when a new input value is stored as the output value. Some flip-flops are rising edge-triggered, and transfer the input value to an output of the flip-flop when the rising edge of the clock signal occurs. Other flip-flops are falling edge-triggered, and transfer the input value to the output on the falling edge of the clock signal. Still other flip-flops are triggered on both the rising edge and falling edge of a clock signal.
Outputs of flip-flops are routed through combinational logic, and supplied to the input of other flip-flops, where a value based on the output of the first flip-flop is latched into the second flip-flop on the next active clock edge. In sequential logic, the input of a flip-flop is determined in part by the value latched into the output of the same flip-flop, so that the next value of a flip-flop depends on the present value of the flip-flop. For the output value of one flip-flop to properly be reflected in the latched output of a second flip-flop, the two flip-flops operate using a common clock edge of a common clock signal. The common clock edge triggers the second flip-flop to latch in the input from the first flip-flop at approximately the same time that the first flip-flop changes the output signal to the second flip-flop. Due to propagation delay between the two flip-flops, the second flip-flop latches in the old value before a new value output by the first flip-flop reaches the second flip-flop.
Electronic circuits using flip-flops which operate on a common clock edge are synchronous. A synchronous circuit is a digital circuit in which the parts are synchronized by a clock signal. Many digital circuits are fully synchronous with a global clock signal driving each part of the circuit. When multiple semiconductor packages are provided on PCB 52, a manufacturer of electronic device 50 provides for communication between the semiconductor packages using traces 54. Traces 54 are connected between semiconductor packages to allow one semiconductor package to utilize functionality provided by circuitry of another semiconductor package. A common clock signal is distributed to each semiconductor package to allow synchronous communication between the packages.
FIG. 2a illustrates a clock distribution network for electronic device 50. Oscillator 80 is a quartz piezo-electric oscillator, although inductor-capacitor (LC) or resistor-capacitor (RC) resonators are used in some embodiments. In other embodiments, any method of generating a clock signal is used. Oscillator 80 creates a periodic, oscillating electronic signal which is sent to fan-out clock buffer 82 via a trace 54. Fan-out buffer 82 includes an amplifier which feeds the signal back to oscillator 80, causing the oscillator to resonate.
Fan-out buffer 82 outputs the clock signal from oscillator 80 to a plurality of output pins or terminals on the package of the fan-out buffer. Traces 54 route the clock signal to the different semiconductor chips and packages of electronic device 50. Each clock signal to each semiconductor package is generated by oscillator 80 and in sync when the signals leave fan-out buffer 82. Fan-out buffer 82 includes a buffer at the output of each clock signal so that each clock output is powered separately and can handle a similar load.
Each semiconductor package receives the clock signal with a common clock edge which occurs approximately simultaneously. The layout of electronic device 50 is designed so that the propagation delay between fan-out buffer 82 and each semiconductor package is approximately the same. One way to accomplish similar propagation delays is to use traces 54 connecting fan-out buffer 82 to each package which are approximately the same length.
Using a common clock signal for each semiconductor package allows synchronous logic on one of semiconductor packages 56-74 to communicate with synchronous logic on another of the semiconductor packages directly using traces 54. Traces 54 run between the semiconductor packages and include lines for address, data, read, write, and other signals needed for the particular semiconductor devices to communicate synchronously.
To help synchronous logic in one semiconductor package communicate with synchronous logic in another semiconductor package, the clock signals which drive the actual flip-flops of each chip should be synchronized. Even though two clock signals may be synchronized entering two different semiconductor packages, the paths a clock signal uses within the chips may cause the propagation delay to some flip-flops to be different than other flip-flops. Different propagation delays internal to two different semiconductor packages results in the flip-flops of the packages being driven by clock edges occurring at different times, making synchronous communication difficult without violating setup and hold times of the flip-flops.
FIG. 2b illustrates a clock tree 90 of semiconductor package 74 as an example. Clock tree 90 receives a clock signal from fan-out buffer 82 at clock input pin 92. Buffers 100-106 distribute the clock signal to flip-flops 107-110. Multiple stages of buffers are used to limit the total load on each individual buffer. While only four total flip-flops and one flip-flop per buffer are illustrated, a single clock tree may include many more than four flip-flops, and multiple flip-flops may receive a clock signal from a single buffer. A clock tree may also provide the clock signal to other types of logic elements besides flip-flops. In other embodiments, clock distribution networks are used which do not follow a tree topology.
Clock tree 90 routes a clock signal throughout semiconductor package 74 to drive the synchronous logic of the semiconductor device. Clock tree 90 injects a certain amount of propagation delay between clock input pin 92 and flip-flops 107-110. Propagation delay is the amount of time between when a clock signal at clock input pin 92 changes and when the clock signal change occurs at flip-flops 107-110. Each buffer 100-106 takes time for a clock signal change at the input of the buffer to be reflected at the output of the buffer. In addition, the clock signal requires a certain amount of time to travel between buffers 100-106 and to flip-flops 107-110 on the illustrated conductive lines.
Each flip-flop 107-110 receives a clock signal from clock input 92 with approximately the same amount of propagation delay due to clock tree 90 being balanced. Clock tree 90 is balanced because the path a clock signal travels to each flip-flop is approximately the same length, and includes the same number of similar buffers. Flip-flops 107-110 communicate with each other synchronously without significant risk of hold time or setup time violations. However, flip-flops in other clock trees, or on other semiconductor devices, should include similar amounts of propagation delay as clock tree 90, or be otherwise synchronized, for reliable synchronous communication.
FIG. 2c illustrates LGA 66 which is a central processing unit (CPU). CPU 66 includes clock input pin 112 connected to buffer 120. Buffers 120-126 form a portion of a clock tree for CPU 66, distributing a clock signal on clock input pin 112 to cache module 128, arithmetic logic unit (ALU) 130, registers 132, and input-output (I/O) block 134. Each of the different blocks 128-134 of CPU 66 includes a clock tree similar to clock tree 90 of FIG. 2b. 
Due to the varied sizes and total amount of flip-flops in blocks 128-134 of CPU 66, the clock trees within each block are different sizes and contribute different amounts of propagation delay between clock input pin 112 and flip-flops of the respective block. Similarly, clock trees in different chips of electronic device 50 include clock trees with different propagation delays. When different propagation delays result in a clock signal arrives at different areas of synchronous logic at different times, clock skew occurs. Clock skew makes synchronous communication between multiple chips, or between multiple modules of a single chip, more difficult. The speed of the clock may need to be slowed down to ensure the hold times and setup times of all flip-flops are observed. Setup time is the amount of time an input signal to a flip-flop must be held at a desired input value prior to the triggering edge of a clock signal to ensure the input value is properly latched to the output of the flip-flop. Hold time of a flip-flop is the amount of time an input to the flip-flop must be held stable after a clock edge to ensure proper operation.
The flip-flops of different chips, and different modules within chips, can be synchronized by balancing the paths of the clock signals to each flip-flop of electronic device 50. While a designer of electronic device 50 can make traces 54 which carry the clock signal to each semiconductor package approximately the same length to balance the propagation delays to each chip, balancing the internal propagation delays between modules of a single chip is more difficult because of the varying sizes and number of flip-flops within different modules. Ensuring a nearly uniform propagation delay among the modules of different semiconductor packages that must communicate synchronously is also difficult. Two chips being used for electronic device 50 may be designed by different manufacturers, with clock propagation delays out of the control of the designer of electronic device 50.
To simplify synchronous communication between different semiconductor devices and clock trees, semiconductor device manufacturers attempt to align edges of a clock signal used by flip-flops of a device with edges of the clock input to the device. FIG. 3 illustrates a clock tree 150 including a clock feedback output which allows another module to observe when a clock edge used by flip-flops of the clock tree occurs. A clock input 152 feeds a clock signal to the clock tree. Buffers 154-159 branch out to provide a clock signal to flip-flops 161-163. Buffer 160 drives clock feedback output port 166. While three flip-flops are illustrated, a clock tree may have more than three flip-flops, and more than one flip-flop may be driven by a single buffer. Flip-flops 161-163 receive clock signals with edges approximately synchronized due to clock tree 150 being properly balanced. However, output signals from flip-flops 161-163 may be routed to flip-flops in other clock trees, and signals from other clock trees may be routed to the inputs of flip-flops 161-163. The other clock trees connected to clock tree 150 do not necessarily include a propagation delay similar to the propagation delay of clock tree 150.
Clock feedback port 166 outputs a clock signal from the clock tree which has clock edges synchronized with edges of the clock signal received by flip-flops 161-163. That is, clock tree 150 is balanced so that the propagation delay between clock input 152 and flip-flops 161-163 is approximately the same as the propagation delay between clock input 152 and clock feedback port 166. Manufacturers use the clock output from clock feedback port 166 to compare the clock used by flip-flops 161-163 with the clock being used by flip-flops in other clock trees, or with a clock signal received by a terminal on the semiconductor device. Modern semiconductor devices include modules which compare clock signals, and adjust the timing of the clock signal at clock input 152 to synchronize the clocks being used by flip-flops in different areas of a chip or different chips on a board.
Manufacturers of electronic and semiconductor devices would like to ensure that different areas of synchronous logic are operating on a common clock edge which occurs at nearly the same time for all flip-flops running on the same clock source. One difficulty is accounting for a wide variation in clock propagation delays and frequencies while maintaining accurate alignment of the clock edges. Comparing two clock signals is difficult at lower frequencies, or when the clock signals are misaligned by greater margins. A method of aligning clock signals which is highly accurate at aligning two clock signals to a common clock edge is not able to quickly and easily align two clocks which are out of phase by a wide margin.